Last updated on 10/2021. For latest ones, please check out PRIME website at https://tangresearch.top/

[J26]. Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, and Shaolan Li, “A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation,” IEEE Journal of Solid-State Circuits, early access.

[J25]. Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, and Nan Sun, “A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4x Passive Gain and Second-Order DAC Mismatch Error Shaping,” IEEE Journal of Solid-State Circuits, early access.

[J24]. Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, and Ru Huang, “TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks,” IEEE Transactions on Circuits and Systems I: Regular Papers, early access.

[J23]. Zhichao Tan, Hui Jiang, Huajun Zhang, Xiyuan Tang, Haoming Xin, and Stoyan Nihtianov, “Power-Efficiency Evolution of Capacitive Sensor Interfaces,” IEEE Sensors Journal, vol. 21, no. 11, pp. 12457-12468, June, 2021.

[J22]. Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun and David Z. Pan, “MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII,” IEEE Design & Test, vol. 38, no. 2, pp. 19-26, Apr. 2021.

[J21]. Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Jr., and Nan Sun, “A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 739-749, Mar. 2021 (CICC invited submission).

[J20]. Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, and Nan Sun, “A 74.5 dB Dynamic Range 10 MHz BW CT-ΔΣ ADC with Distributed-Input VCO and Embedded Capacitive-π Network in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 476-487, Feb. 2021.

[J19]. Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13-bit 0.005-mm2 40-MS/s SAR ADC with kT/C Noise Cancellation,” IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3260-3270, Dec. 2020 (ISSCC invited submission).

[J18]. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, and Nan Sun, “A 13.5-ENOB, 107-uW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3248-3259, Dec. 2020 (ISSCC invited submission).

[J17]. Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, and Nan Sun, “An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 55, no. 11, pp. 3064-3075, Nov. 2020.

[J16]. Hao Chen*, Mingjie Liu*, Xiyuan Tang*, keren Zhu*, Nan Sun, and David Z. Pan, “Challenges and opportunities toward fully automated analog layout design,” Journal of Semiconductors, vol. 41, no. 11, pp. 1407, Nov. 2020 (*: Equal contribution).

[J15]. Jiaxin Liu, Xiyuan Tang, Linxiao Shen, Shaolan Li, Zhelu Li, Wenjuan Guo, and Nan Sun, “Error suppression techniques for energy-efficient high-resolution SAR ADCs,” Journal of Semiconductors, vol. 41, no. 11, pp. 1403, Nov. 2020.

[J14]. Abhishek Mukherjee, Xiyuan Tang, Chen-Kai Hsu, and Nan Sun, “Design Tradeoffs for a CT-ΔΣ ADC with Hybrid Active-Passive Filter and FIR DAC in 40 nm CMOS,” IEEE Solid-State Circuits Letters, vol. 3, pp. 214-217, 2020.

[J13]. Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, and Nan Sun, “An Energy-Efficient Comparator with Dynamic Floating Inverter Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, Apr. 2020 (VLSI invited submission).

[J12]. Yi Shen, Xiyuan Tang*, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Xin Xin, Shubin Liu, Visvesh Sathe, and Nan Sun, “A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 680-692, Mar. 2020 (CICC invited submission; *Corresponding author).

[J11]. Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, and Nan Sun, “A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 666-679, Mar. 2020 (CICC invited submission).

[J10]. Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, and Nan Sun, “A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 602-614, Mar. 2020 (CICC invited submission).

[J9]. Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, and Nan Sun, “Second-Order Purely VCO-Based CT ADC Using a Modified DPLL Structure in 40-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 356-368, Feb. 2020.

[J8]. Linxiao Shen, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu, and Nan Sun, “A Two-Step ADC with a Continuous-Time SAR Based First Stage,” IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3375-3385, Dec. 2019 (ISSCC invited submission).

[J7]. Abhishek Mukherjee, Miguel Gandara, Biying Xu, Shaolan Li, Linxiao Shen, Xiyuan Tang, David Z. Pan, and Nan Sun, “A 1 GS/s 20 MHz-BW Capacitive-Input Continuous Time ∆Σ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO,” IEEE Solid-State Circuits Letters, vol. 2, no. 1, pp.1-4.

[J6]. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, and Nan Sun, “A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC with Mean Absolute Deviation Based Background Timing-Skew Calibration,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2876-2887, Aug. 2019.

[J5]. Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, and Nan Sun, “Advances in Voltage-Controlled-Oscillator-Based ∆Σ ADCs,” IEICE Transactions on Electronics, vol. 102, no. 7, pp. 509-519, 2019.

[J4]. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, and Nan Sun, “Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters,” IEEE Transactions on Circuits and Systems – I: Regular Papers (TCAS-I), vol.66, no.4, pp. 1343-1354, Apr. 2019.

[J3]. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, and Nan Sun, “A 10-b 800MS/s Time-Interleaved SAR ADC with Fast Variance-Based Timing-Skew Calibration,” IEEE Journal of Solid-State Circuits (ASSCC invited submission), vol. 52, no. 10, pp. 2563-2575, Oct. 2017.

[J2]. Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, and Nan Sun, “A 0.7V 0.6μW 100kS/s Low-Power SAR ADC with Statistical Estimation Based Noise Reduction,” IEEE Journal of Solid-State Circuits, vol. 52, No. 5, pp. 1388-1398, May 2017.

[J1]. Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, and Nan Sun, “A 0.95-mW 6-b 700-Ms/s single-channel loop-unrolled SAR ADC in 40-nm CMOS,” IEEE Transactions on Circuits and Systems – II: Express Briefs, vol.PP, No.99, pp.1-14, Feb. 2017.

[C41]. Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun and David Z. Pan, “OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021.

[C40]. Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan, “Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks,” ACM/IEEE Design Automation Conference (DAC), July 2021.

[C39]. Hao Chen*, Mingjie Liu*, Xiyuan Tang*, Keren Zhu*, Abhishek Mukherjee, Nan Sun, and David Z. Pan, “MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s ∆Σ ADC,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021 (*: Equal contribution).

[C38]. Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, and Nan Sun, “An 81.5dB-DR 1.25MHz-BW VCO-Based CT ∆Σ ADC with Double-PFD Quantizer,”
IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021.

[C37]. Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, and Nan Sun, “An In-Memory-Computing Charge-Domain Ternary CNN Classifier,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021.

[C36]. Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, and Nan Sun, “A 0.4-to-40MS/s 75.7dB-SNDR Fully-Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.

[C35]. Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, and Nan Sun, “A 3.7mW 12.5MHz 81dB-SNDR 4th-order CTDSM with Single-OTA and 2nd-order NS-SAR,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.

[C34]. Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, and Nan Sun, “A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.

[C33]. Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, and Nan Sun, “Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC,”
IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2020.

[C32]. Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan, “Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits,”
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020.

[C31]. Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan, “Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020.

[C30]. Yuxuan Huang, Qinghang Zhao, Xiyuan Tang, Fang Su, Nan Sun, Huazhong Yang, and Yongpan Liu, “An Energy-Efficient Flexible Capacitive Pressure Sensing System,” IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020.

[C29]. Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, and Nan Sun, “A 10-bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation,” IEEE Symposium on VLSI Circuits (VLSI), June 2020.

[C28]. Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, and Nan Sun, “A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW,” IEEE Symposium on VLSI Circuits (VLSI), June 2020.

[C27]. Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun and David Z. Pan, “Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.

[C26]. Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy Andeen, and Nan Sun, “A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping,” IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020.

[C25]. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, and Nan Sun, “A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 162-164, Feb. 2020 (ISSCC Highlight).

[C24]. Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13-bit 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 258-260, Feb. 2020.

[C23]. Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, and Nan Sun, “A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-order Mismatch Error Shaping,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 158-160, Feb. 2020.

[C22]. Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z. Pan, “Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning,” IEEE/ACM Design, Automation & Test in Europe (DATE), 2020.

[C21]. Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan, “S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, Jan. 13-16, 2020.

[C20]. Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun and David Z. Pan, “GeniusRoute: A New Routing Paradigm Using Generative Neural Network Guidance for Analog Circuits,” IEEE/ACM International Conference on Computer-Aided Design (IC-CAD), Westminster, CO, Nov. 4-7, 2019.

[C19]. Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan, “MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence,” IEEE/ACM International Conference on Computer-Aided Design (IC-CAD), Westminster, CO, Nov. 4-7, 2019. (Invited Paper)

[C18]. Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, and Nan Sun, “An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier,” IEEE Symposium on VLSI Circuits (VLSI), pp. C140-C141, June 2019. (VLSI STGA Award)

[C17]. Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, and Nan Sun, “A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF,” IEEE Symposium on VLSI Circuits (VLSI), pp. C144-C145, June 2019.

[C16]. Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe and Nan Sun, “A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

[C15]. Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan and Nan Sun, “A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL-DSM ,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

[C14]. Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng and Nan Sun, “A 2.4-GHz DS Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

[C13]. Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, and David Z. Pan, “WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout,” ACM/IEEE Design Automation Conference (DAC), pp. 66-1, Jun. 2019.

[C12]. Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal Hall, and Nan Sun, “A 16fJ/conversion-step Time-Domain Two-step Capacitance-to-Digital Converter,” IEEE international Solid-State Circuits Conference (ISSCC), pp. 296-297. Feb. 2019. (ISSCC STGA Award)

[C11]. Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, and Nan Sun, “A 0.01mm2 25uW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor,” IEEE international Solid-State Circuits Conference (ISSCC), pp. 64-66, Feb. 2019.

[C10]. Mohamed Baker Alawieh, Xiyuan Tang, and David Z. Pan, “Semi-Supervised Learning for Effcient Performance Modeling of Analog and Mixed Signal Circuits,” ACE/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 268-273, Jan. 2019.

[C9]. Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, and Nan Sun, “A Second-Order Purely VCO-Based CT DS ADC Using a Modified DPLL in 40-nm CMOS,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 93-94, Nov. 2018.

[C8]. Xiyuan Tang, Long Chen, Jeonggoo Song, and Nan Sun, “A 1.5fJ/Conv-step 10b 100kS/s SAR ADC with Gain-Boosted Dynamic Comparator,” IEEE Asian Solid-State Circuits Conference (ASSCC), 2017, pp. 219-232.

[C7]. Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, and Nan Sun, “A Pipelined SAR ADC Reusing the Comparator as Residue Amplifier,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2017.

[C6]. Jeonggoo Song, Xiyuan Tang, and Nan Sun, “A 10-b 2b/cycle 300MS/s SAR ADC with a Single Differential DAC in 40nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2017.

[C5]. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, and Nan Sun, “A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 73-76, Nov. 2016.

[C4]. Xiyuan Tang, Long Chen, Jeonggoo Song, and Nan Sun, “A 10-b 750μW 200MS/s Fully Dynamic Single-Channel SAR ADC in 40nm CMOS,” IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 413-416, Sept. 2016.

[C3]. Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, and Nan Sun, “Comparator common-mode variation effects analysis and its application in SAR ADCs,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2014-2017, May 2016.

[C2]. Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, and Nan Sun, “A 10.5-b ENOB 645nW 100kS/s SAR ADC with Statistical Estimation Based Noise Reduction,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, Sept. 2015.

[C1]. Yeonam Yoon, Koungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, and Nan Sun, “A 0.04-mm2 Modular ∆Σ ADC with VCO-based Integrator and 0.9-mW 71-dB SNDR Distributed Digital DAC Calibration,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, Sept. 2015.

Xiyuan Tang, Nan Sun “Time-domain capacitance-to-digital converter,” US Patent 17,176,341, 2021.

Nan Sun, Long Chen, Xiyuan Tang, “Statistical estimation based noise reduction technique for low power successive approximation register analog-to-digital converter,", US Patent 20,170,093,414, 2017.