Journal Articles

Conference Papers

  • [C29]. Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, and Nan Sun, “A 10-bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation,” IEEE Symposium on VLSI Circuits (VLSI), Jun. 2020, accepted.

  • [C28]. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, and Nan Sun, “A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020, accepted.

  • [C27]. Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, and Nan Sun, “An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier,” IEEE Symposium on VLSI Circuits (VLSI), pp. C140-C141, June 2019. (VLSI STGA Award)

  • [C26]. Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe and Nan Sun, “A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

  • [C25]. Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal Hall, and Nan Sun, “A 16fJ/conversion-step Time-Domain Two-step Capacitance-to-Digital Converter,” IEEE international Solid-State Circuits Conference (ISSCC), pp. 296-297. Feb. 2019. (ISSCC STGA Award)

  • [C24]. Xiyuan Tang, Long Chen, Jeonggoo Song, and Nan Sun, “A 1.5fJ/Conv-step 10b 100kS/s SAR ADC with Gain-Boosted Dynamic Comparator,” IEEE Asian Solid-State Circuits Conference (ASSCC), 2017, pp. 219-232.

  • [C23]. Xiyuan Tang, Long Chen, Jeonggoo Song, and Nan Sun, “A 10-b 750μW 200MS/s Fully Dynamic Single-Channel SAR ADC in 40nm CMOS,” IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 413-416, Sept. 2016.

  • [C22]. Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, and Nan Sun, “A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW,” IEEE Symposium on VLSI Circuits (VLSI), Jun. 2020, accepted.

  • [C21]. Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun and David Z. Pan, “Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020, accepted.

  • [C20]. Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy Andeen, and Nan Sun, “A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping,” IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020, accepted.

  • [C19]. Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13-bit 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020, accepted.

  • [C18]. Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, and Nan Sun, “A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-order Mismatch Error Shaping,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020, accepted.

  • [C17]. Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z. Pan, “Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning,” IEEE/ACM Design, Automation & Test in Europe (DATE), 2020, accepted.

  • [C16]. Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan, “S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity,” IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, Jan. 13-16, 2020, accepted.

  • [C15]. Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun and David Z. Pan, “GeniusRoute: A New Routing Paradigm Using Generative Neural Network Guidance for Analog Circuits,” IEEE/ACM International Conference on Computer-Aided Design (IC-CAD), Westminster, CO, Nov. 4-7, 2019.

  • [C14]. Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan, “MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence,” IEEE/ACM International Conference on Computer-Aided Design (IC-CAD), Westminster, CO, Nov. 4-7, 2019. (Invited Paper)

  • [C13]. Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, and Nan Sun, “A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF,” IEEE Symposium on VLSI Circuits (VLSI), pp. C144-C145, June 2019.

  • [C12]. Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan and Nan Sun, “A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL-DSM ,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

  • [C11]. Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng and Nan Sun, “A 2.4-GHz DS Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Apr. 2019.

  • [C10]. Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, and David Z. Pan, “WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout,” ACM/IEEE Design Automation Conference (DAC), pp. 66-1, Jun. 2019.

  • [C9]. Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, and Nan Sun, “A 0.01mm2 25uW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor,” IEEE international Solid-State Circuits Conference (ISSCC), pp. 64-66, Feb. 2019.

  • [C8]. Mohamed Baker Alawieh, Xiyuan Tang, and David Z. Pan, “Semi-Supervised Learning for Effcient Performance Modeling of Analog and Mixed Signal Circuits,” ACE/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 268-273, Jan. 2019.

  • [C7]. Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, and Nan Sun, “A Second-Order Purely VCO-Based CT DS ADC Using a Modified DPLL in 40-nm CMOS,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 93-94, Nov. 2018.

  • [C6]. Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, and Nan Sun, “A Pipelined SAR ADC Reusing the Comparator as Residue Amplifier,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2017.

  • [C5]. Jeonggoo Song, Xiyuan Tang, and Nan Sun, “A 10-b 2b/cycle 300MS/s SAR ADC with a Single Differential DAC in 40nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2017.

  • [C4]. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, and Nan Sun, “A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 73-76, Nov. 2016.

  • [C3]. Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, and Nan Sun, “Comparator common-mode variation effects analysis and its application in SAR ADCs,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2014-2017, May 2016.

  • [C2]. Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, and Nan Sun, “A 10.5-b ENOB 645nW 100kS/s SAR ADC with Statistical Estimation Based Noise Reduction,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, Sept. 2015.

  • [C1]. Yeonam Yoon, Koungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, and Nan Sun, “A 0.04-mm2 Modular ∆Σ ADC with VCO-based Integrator and 0.9-mW 71-dB SNDR Distributed Digital DAC Calibration,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, Sept. 2015.